The present invention relates in general to integrated circuits, and in particular to an improved voltage pump circuit that reduces stress on transistor gate oxide layer.
Charge pump techniques allow integrated circuits to internally generate voltage levels that are higher (or lower) than the externally supplied voltage source. One example of a circuit that requires voltages higher than the supply voltage is the electrically erasable programmable read only memory (EEPROM). EEPROM devices require programming voltage Vpp levels that are higher in value (e.g., 13 volts) than the normal power supply voltage level Vcc (e.g., 5 volts). In such devices, it is often necessary to boost the level at certain nodes inside the circuit to voltages even higher than Vpp. For example, to selectively transfer a full Vpp voltage level into a target cell via a pass transistor, the gate of the pass transistor requires a boosted voltage level even higher than Vpp. Therefore, Vpp is used in additional charge pump circuitry to generate boosted voltages (e.g., 15.5 v) on the word lines.
Under such conditions, transistors involved in the word line boost and driver circuitry experience much higher voltages than other transistors and are thus subject to higher stress. Over time, this stress leads to degradation of the thin oxide layer forming the gate dielectric in the MOS transistors.
FIG. 1 shows one example of a prior art word line driver circuit. In this circuit, when the enable signal EN is at a logic high level (e.g., at Vcc), the voltage on the word line WL is pumped to the smaller of [Vpp+(K*Vcc)-Vtnat] or Vpp+Vt(MN1), where the value of K can be adjusted by the designer, and Vtnat is the threshold voltage of the native device MNN2. When enable signal EN is at a logic low level (e.g., ground), the voltage on WL is also at the logic low level or ground. This causes the gate oxide for transistor MNN1 and MN1 to experience voltages as high as Vpp. With an exemplary oxide thickness value of 145 Angstroms, a Vpp of about 13 volts places transistor MNN1 and MN1 under excessive voltage stress when EN is at ground.
As the MOS transistor geometries continue to shrink with advances in semiconductor processing technology, oxide stress has become a much more serious reliability issue.